Zilog Z08470 User Manual
Page 273
Z80 CPU Peripherals
User Manual
UM008101-0601
Serial Input/Output
253
WR0
Pointer 1, Reset External/Status
Interrupt
WR1
Status Affects Vector, External
Interrupt Enable, Receive Interrupt on
first character only
In this interrupt mode, only the first
non-sync data character is transferred to
the CPU. All subsequent data is
transferred on a DMA basis; however,
special receive condition interrupts
interrupt the CPU. status affects vector
used in Channel B only.
WR0
Pointer 3, Enable Interrupt on next
Receive character
Resetting this Interrupt Mode provides
simple program loopback entry for the
next transaction.
WR3
Receive Enable, sync character load
inhibit, enter Hunt Mode Auto Enable,
receive word length
WR3 is reissued to enable receiver;
receive CRC enable must be set after
receiving SOH or STX character.
Idle Mode
Execute Halt Instruction or some other
program
Receive mode is fully initialized and the
system is waiting for interrupt on first
character.
Table 7. Bisync Receive Mode (Continued)
Function
Typical Program Steps
Comments