Zilog Z08470 - Manual (Page 192)

< %27 2GTKRJGTCNU
7UGT /CPWCN
UM008101-0601 Direct Memory Access
Figure 81. Write Register 5 Group
Figure 82. Write Register 6 Group
D7 D6 D5 D4 D3 D2 D1 D0
Base Register Byte
0 = Ready Active Low
1 = Ready Active High
1 0 0 1 0
0 = Stop on End-of-Block
1 = Auto Restart on End-of-Block
0 = CE Only
1 = CE/WAIT Multiplexed
D7 D6 D5 D4 D3 D2 D1 D0
Base Register Byte
0 1
1 1 1
= C3 = Reset 0 0 0
Hex Command Name
0 1 = C7 = Reset Port A Timing 0 0 1
0 1 = C8 = Reset Port B Timing 0 1 0
0 1 = CF = Load 0 1 1
0 1 = D3 = Continue 1 0 0
1 0 = AF = Disable Interrupts 0 1 1
1 0 = AB = Enable Interrupts 0 1 0
1 0 = A3 = Reset and Disable Interrupts 0 0 0
1 0 = B7 = Enable after RETI 1 0 1
1 0 = BF = Read Status Byte 1 1 1
0 0 = 8B = Reinitialize Status Byte 0 1 0
1 0 = A7 = Initialize Read Sequence 0 0 1
1 0 = B3 = Force Ready 1 0 0
0 0 = 87 = Enable DMA 0 0 1
0 0 = 83 = Disable DMA 0 0 0
1 0 = BB = Read Mask Follows 1 1 0
Base Register Byte
Status Byte
Byte Counter (Low Byte)
Byte Counter (High Byte)
Port A Address (Low Byte)
Port B Address (High Byte)
0
Port B Address (Low Byte)
Port A Address (High Byte)