Zilog Z08470 - Manual (Page 144)

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UM008101-0601 Direct Memory Access
Variable Timing
The timing on the RD, WR, MREQ, and IORQ lines can be varied indepen-
dently for either port by programming the WR1 and/or WR2 register groups.
When programming memory-to-I/O, I/O-to-memory, or I/O-to-I/O
sequential transfers or transfer/searches, the IORQ line must be programmed
in a specific way. See “Variable Cycle (Port A)” on page 96.
Enabling the DMA
The last command written to the DMA before an operation occurs must be
the
ENABLE DMA command, or WR3 bit 6 = 1, which is equivalent. Only
this command makes the DMA operate. If all other conditions for operation
are satisfied at the time of enabling (for example, the Ready line is active)
the DMA begins immediately. In an interrupt service routine, the
ENABLE
DMA command must be the last DMA command written before the return
from-interrupt instruction. Other instructions usually follow the ENABLE
DMA command in the service routine before the RETI instruction is
executed, but none of these commands affect the DMA.
Reading Status
These two commands allow the CPU to read DMA status:
READ STATUS BYTE
Causes the next CPU read of the DMA to access the status byte. Every time
the status byte is to be read, the
READ STATUS BYTE command must first be
written.
INITIATE READ SEQUENCE
Causes the next CPU read of the DMA to access the first status register
specified as readable by the read mask. Subsequent reads of the DMA,
which must complete the sequence of all designated readable registers, do
not require write commands. Reading of the sequence of registers must be