Zilog Z08470 - Manual (Page 185)

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UM008101-0601 Direct Memory Access
Figure 73. Variable-Cycle and Edge Timing
In the Variable-Cycle mode, unlike default tuning, IORQ comes active one-
half cycle before MREQ, RD, and WR. CE/WAIT can be used to extend
only the 3 or 4 clock cycle variable memory cycles and only the 4-cycle
variable I/O cycle (see Figure 75). The CE/WAIT line is sampled at the
falling edge of T2 for 3- or 4-cycle memory operations, and at the falling
edge of T3 for 4-cycle I/O operations. The line is not sampled for 2-cycle
operations. During transfers, data is latched on the clock edge, causing the
rising edge of RD and held until the end of the write cycle.
Using variable timing on an I/O-search, a simultaneous transfer, or transfer/
search with I/O as the source port, creates a unique situation. In these appli-
cations, the IORQ line must be programmed to end early. See “Write Regis-
ter 1 Group” on page 96. The simultaneous transfers are programmed in the
DMA as searches and are only distinguished from searches by the way
external logic handles the bus control signals.
Figure 72 illustrates the bus control lines (MREQ and RD) remaining inac-
tive when the RDY line goes inactive in Continuous mode. The same is not
true of the IORQ line when variable timing is used. In this instance, IORQ
CLK
IORQ
A15–A0
T
1
T
2
T
3
T
4
MREQ
RD, WR
2-Cycle
Early End
3-Cycle
Early End
4-Cycle
Early End