Zilog Z08470 - Manual (Page 172)

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UM008101-0601 Direct Memory Access
Simultaneous Transfers
The timing for simultaneous transfers and simultaneous transfer/searches is
the same. The DMA is programmed in the Search-Only mode, and both
read and write cycles occur simultaneously in the time that a source-port
read would occur in search-only. Only one address is generated on the
address bus; the I/O port is hardwire-selected during this operation as
shown in the Applications chapter. The IORQ, MREQ, RD, and WR lines
are gated into two new signals by external logic. These signals are either:
MEMWR (Memory write)
IORD (I/O read)
or:
MEMRD (Memory read)
IOWR (I/O write)