Zilog Z08470 - Manual (Page 243)

Z80 CPU Peripherals
User Manual
UM008101-0601 Serial Input/Output
223
Data Path
The transmit and receive data path for each channel is depicted in
Figure 109 . The receiver contains three 8-bit buffer registers in a FIFO
arrangement (to provide a 3-byte delay) in addition to the 8-bit receive shift
register. This arrangement creates additional time for the CPU to service an
interrupt at the beginning of a block of high-speed data. The receive error
FIFO stores parity and framing errors and other types of status information
for each of the three bytes in the receive data FIFO.
Incoming data is routed through one of several paths depending on the
mode and character length. In the Asynchronous mode, serial data is
Table 1. Write Register Functions
Bit Function
WR0 Register pointers, CRC initialize, initialization commands for the
various modes and more
WR1 Transmit/Receive interrupt and data transfer mode definition
WR2 Interrupt vector (Channel B only)
WR3 Receive parameters and controls
WR4 Transmit/Receive miscellaneous parameters and modes
WR5 Transmit parameters and controls
WR6 Sync character or SDLC address field
WR7 Sync character or SDLC flag
Table 2. Read Register Functions
Bit Function
RR0 Transmit/Receive buffer status, interrupt status, and external status
RR1 Special Receive Condition status
RR2 Modified interrupt vector (Channel B only)