Zilog Z08470 - Manual (Page 189)

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7UGT /CPWCN
UM008101-0601 Direct Memory Access
REGISTER BIT FUNCTIONS
Write Register Bit Functions
Figure 76. Write Register 0 Group
Figure 77. Write Register 1 Group
D7 D6 D5 D4 D3 D2 D1 D0
Base Register Byte
Port A Starting Address
0 0
0
1
1 1
0
1
Do not use
= Transfer
= Search
= Search/Transfer
0 = Port B
→
Port A
0 = Port A
→
Port B
(Low Byte)
Port A Starting Address
(High Byte)
Block Length
(Low Byte)
Block Length
(High Byte)
D7 D6 D5 D4 D3 D2 D1 D0
Base Register Byte
0 0
0
1
1 1
0
1
= Port A Address Decrements
0 = Port A is Memory
0 = Port A is I/O
Port A Variable
0 0
0
1
1 1
0
1 = Cycle Length = 3
= Cycle Length = 2
= Do Not Use
= Port A Address Increments
= Port A Address Fixed
Timing Byte
= Cycle Length = 4
WR Ends 1/2 Cycle Early = 0
RD Ends 1/2 Cycle Early = 0
MREQ Ends 1/2 Cycle Early = 0 0 = IORQ Ends 1/2 Cycle Early
0 0
0 0 1 0