Zilog Z08470 - Manual (Page 271)

Z80 CPU Peripherals
User Manual
UM008101-0601 Serial Input/Output
251
before the next character is transferred, CRC is calculated on the transferred
character. If CRC is disabled before the time of the next transfer, calcula-
tion proceeds on the word in progress, but the word just transferred to the
buffer is not included. When these requirements are satisfied, the 3-byte
receive data buffer is, in effect, unusable in Bisync operation. CRC may be
enabled and disabled as many times as necessary for a given calculation.
In the Monosync, Bisync, and External Sync modes, the CRC/Framing Error
bit (RR1, D6) contains the comparison result of the CRC checker 16-bit
times (eight bits delay and eight shifts for CRC) after the character has been
transferred from the receive shift register to the buffer. The result should be
zero, indicating an error-free transmission.
The result is valid only at the end of CRC calculation. If the result
is examined before this time, it usually indicates an error.
The comparison is made with each transfer and is valid only as long as the
character remains in the receive FIFO.
Following is an example of the CRC checking operation when four charac-
ters (A, B, C, and D) are received in that order.
•
Character A loaded to buffer
•
Character B loaded to buffer
If CRC is disabled before C is in the buffer, CRC is not calculated on B.
•
Character C loaded to buffer
After C is loaded, the CRC/Framing Error bit shows the result of the
comparison through character A.
•
Character D loaded to buffer
After D is in the buffer, the CRC Error bit shows the result of the comparison
through character B whether or not B was included in the CRC calculations.
Due to the serial nature of CRC calculation, the Receive Clock (RxC)
must cycle 16 times (8-bit delay plus 8-bit CRC shift) after the second
Note: