Zilog Z08470 - Manual (Page 115)

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UM008101-0601 Direct Memory Access
In addition, bits 7, 6, 3, and 2 of the variable-timing byte allow termination
of various lines 1/2 cycle earlier than specified in bits 1 and 0. The chapter
on “Timing” illustrates and describes the effect of this in detail.
Particular note must be taken of the IORQ line when variable-cycle timing
is used in sequential transfers or transfer/searches. In I/O-to-memory or
memory-to-I/O operation, the memory port must be programmed to allow
its IORQ line to end early. (The IORQ line normally has nothing to do with
memory). However, this requirement does not apply to the CMOS DMA
counter controller. If an I/O-to-I/O operation is being performed, both ports
must have their IORQ lines end early. When the variable-timing feature is
employed the IORQ line changes logic levels off a different clock cycle
edge than the other control lines.
Figure 41. Write Register 1 Group
D7 D6 D5 D4 D3 D2 D1 D0
Base Register Byte
0 0
0
1
1 1
0
1
= Port A Address Decrements
0 = Port A is Memory
0 = Port A is I/O
Port A Variable
0 0
0
1
1 1
0
1 = Cycle Length = 3
= Cycle Length = 2
= Do Not Use
= Port A Address Increments
= Port A Address Fixed
Timing Byte
= Cycle Length = 4
WR Ends 1/2 Cycle Early = 0
RD Ends 1/2 Cycle Early = 0
MREQ Ends 1/2 Cycle Early = 0 0 = IORQ Ends 1/2 Cycle Early
0 0
0 0 1 0