Zilog Z08470 - Manual (Page 326)

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UM008101-0601 Serial Input/Output
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Figure 129. Write Cycle Timing
Interrupt Acknowledge Cycle
After receiving an Interrupt Request signal, INT pulled Low, the Z80 CPU
sends an Interrupt Acknowledge signal, M1 and IORQ, both Low. The
daisy-chained interrupt circuits determine the highest priority interrupt
requestor. The IEI of the highest priority peripheral is terminated High.
Peripherals that have no interrupt pending or under service are terminated
IEO = IEI. Any peripheral that does have an interrupt pending or under
service, forces its IEO Low.
To insure stable conditions in the daisy-chain, all interrupt status signals are
prevented from changing while MI is Low. When IORQ is Low, the highest
priority interrupt requestor, which is the one with IEI High, places its
interrupt vector on the data bus and sets its internal interrupt-underservice
latch. See Figure 130.
Channel Address
T
1
Φ
CE
IORQ
RD
M1
Data
T
2
T
W
T
3
T
1
In