Zilog Z08470 User Manual
Page 146
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7UGT /CPWCN
UM008101-0601
Direct Memory Access
WR4 sets mode to
Burst and sets DMA
to expect Port B
address
1
1
0
0
No
Interrup
t
Control
Byte
Follows
0
No
Upper
Address
1
Port B
Lower
Address
Follows
0
1
C5
Port B address
(lower)
0
0
0
0
0
1
0
1
05
WR5 sets Ready
active High
1
0
0
No
Auto
Restart
0
No Wait
Status
1
RDY
Active
High
0
1
0
8A
WR6 loads Port B
address and resets
block counter *
1
1
0
0
1
1
1
1
CF
WR0 sets Port A as
source *
0
0
0
0
0
1
B
→A
0
1
05
No Address or Block
Length Bytes
Transfer No
Search
WR6 loads Port A
address
and resets block
counter
1
1
0
0
1
1
1
1
CF
WR6 enables DMA
to start operation.
1
0
0
0
0
1
1
1
87
Table 16. Sample DMA Program (Continued)
D7
D5
D4
D3
D2
D1
D0
HEX