Zilog Z08470 - Manual (Page 319)

Z80 CPU Peripherals
User Manual
UM008101-0601 Serial Input/Output
299
Figure 123. Read Register 1
Parity Error (D4)
When parity is enabled, this bit is set for those characters whose parity does
not match the programmed sense (even/odd). The bit is latched, so when an
error occurs, the bit remains set until given the Error Reset command (WR0).
Receive Overrun Error (D5)
This bit indicates that more than three characters have been received
without a read from the CPU. Only the character that has been written over
is flagged with this error, but when this character is read, the error condition
is latched until reset by the Error Reset command. If Status Affects Vector
is enabled, the character that has been overrun interrupts with a Special
Receive Condition vector.
1 0 0
0 1 0
1 1 0
0 0 1
1 0 1
0 1 1
1 1 1
0 0 0
Parity Error
Rx Overrun Error
CRC/Framing Error
End-of-Frame (SDLC)
D7 D6 D5 D4 D3 D2 D1 D0
*Residue Data for Eight Rx
Bits/Character Programmed
All Sent
I Field Bits
in Previous
Byte
0
0
0
0
0
0
1
2
I Field Bits in
Second Previous
Byte
3
4
5
6
7
8
8
8
*