Altera ALTDQ_DQS2 - Manual (Page 99)

Date Version Changes
December 2012 2.0 • Major enhancement to include:
• Arria V and Cyclone V devices information.
• Updated “Features” on page 1–1:
• Included read FIFO, hard FIFO, latency
shifter FIFO, and data valid FIFO.
• “Device Support” on page 1–2
• Included Arria V and Cyclone V devices.
• Updated “Parameter Settings” on page 2–1:
• Updated Table 2–1 on page 2–1 to include
new parameters and to update old
parameters.
• Updated “ALTDQ_DQS2 Datapaths” on
page 3–1:
• Updated Figure 3–1 and added notes (3),
(4), and (5) to clarify the usage of soft and
hard FIFO for different devices and to
explain the location of an inversion.
• Added the following new sections: “DQS
Logic” on page 3–2, “Capture DDIO to Read
FIFO Path” on page 3–3, and “FIFO
Control” on page 3–4.
• Updated “ALTDQ_DQS2 Ports” on page 3–
10:
• Updated “DQ and DQS Output Path” on
page 3–6 to include DQS output path
information.
• Updated Figure 3–5 on page 3–6 and added
notes to the figure to help distinguish the
device support.
• Updated Figure 3–6 on page 3–7 to fix the
variable typo and to clarify that the figure is
for additional pin usage for Stratix V devices.
• Combined and converted IP cores informa‐
tion to Table 3–3 on page 3–8 for ease of
reference.
• Added Figure 3–7 on page 3–8 to shows the
DQ and DQS output path for Arria V and
Cyclone V devices.
UG-01089
2014.12.17
Document Revision History 99
ALTDQ_DQS2 IP Core User Guide Altera Corporation
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