Altera ALTDQ_DQS2 - Manual (Page 8)

Figure 6: IP Core Generated Files
Notes:
1. If supported and enabled for your IP variation
2. If functional simulation models are generated
_sim 1
_instance.vo - IPFS model 2
.qip - Quartus II IP integration file
.sip - Lists files for simulation
_testbench or _example - Testbench or example1
.v, .sv. or .vhd - Top-level IP synthesis file
_instance
_syn.v or .vhd - Timing & resource estimation netlist1
.cmp - VHDL component declaration file
.bsf - Block symbol schematic file
- IP core synthesis files
.sv, .v, or .vhd - HDL synthesis files
.sdc - Timing constraints file
.ppf - XML I/O pin information file
.spd - Combines individual simulation scripts
1
_sim.f - Refers to simulation models and scripts
1
Upgrading IP Cores
IP core variants generated with a previous version of the Quartus II software may require upgrading
before use in the current version of the Quartus II software. Click Project > Upgrade IP Components to
identify and upgrade IP core variants.
The Upgrade IP Components dialog box provides instructions when IP upgrade is required, optional, or
unsupported for specific IP cores in your design. You must upgrade IP cores that require it before you can
compile the IP variation in the current version of the Quartus II software. Many Altera IP cores support
automatic upgrade.
The upgrade process renames and preserves the existing variation file (
.v , . sv , or .vhd ) as _
BAK.v , .sv , .vhd in the project directory.
8 Upgrading IP Cores
UG-01089
2014.12.17
Altera Corporation ALTDQ_DQS2 IP Core User Guide
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