Altera ALTDQ_DQS2 - Manual (Page 81)

Clock Description
outclk_4 200 MHz. Used to drive the ALTDLL IP core. The following are the ALTDLL
minimum frequency:
• Arria V devices: 200 MHZ
• Arria V GZ: 300 MHz
outclk_5 200 MHz. Used to drive the full-rate core clock.
outclk_6 100 MHz. Used to drive the half-rate core clock.
outclk_7 25 MHz. Used as config_clk.
Note: lf the memory frequency is less than the ALTDLL IP core minimum frequency, then drive the
ALTDLL IP core at 2x or 4x of the memory frequency. Relatively, the DQS phase settings decrease
as well.
Setting Up NativeLink and Simulation Settings
To set up the NativeLink and simulation settings, follow these steps:
1. In the Quartus II software, on the Tools menu, select Options.
2. In the Options dialog box, under Category list, expand General and then select EDA Tool Options.
3. In the EDA Tools Options window, follow the settings as shown in the following figure:
Figure 49: EDA Tools Options Dialog Box
4. In the Quartus II software, on the Assignments menu, click Settings.
5. In the Settings dialog box, under the Category list, expand EDA Tool Settings. Click Simulation.
6. Enter the necessary NativeLink settings. The following figure shows an example settings. In this design
example, a testbench (tb.v) is provided together with other supporting files.
UG-01089
2014.12.17
Setting Up NativeLink and Simulation Settings 81
ALTDQ_DQS2 IP Core User Guide Altera Corporation
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