Altera ALTDQ_DQS2 - Manual (Page 47)

Legend in I/O Configu‐
ration Block Bit
Sequence for Arria V
GZ and Stratix V
Devices on page 40
Bit Bit Name Description
P 69 enaoctphasetransferreg Connects to the enaphasetrans‐
ferreg port of the output
alignment block (in the dynamic
OCT control path) to allow an
additional negative edge-
triggered register to be added to
the OCT, output data, or output
enable path to satisfy the setup or
hold time requirement for the
phase transfer.
Q 77..70 dqsdisablendelaysetting Connects to the delayctrlin port
of the T11 delay chain (located
between the dqsenableout port of
the DQS enable control block
and the dqsdisablen port of the
DQS delay chain).
This is to align post-amble signal
in terms of DQS signal by
selecting different delays.
R 85..78 dqsenabledelaysetting Connects to the delayctrlin port
of the T11 delay chain (located
between the dqsenableout port of
the DQS enable control block
and the dqsenable port of the
DQS delay chain).
This is to align post-amble signal
in terms of DQS signal by
selecting different delays.
S 86 enadqsenablephasetransferreg Connects to the enaphasetrans‐
ferreg port of the DQS enable
control block to allow an
additional negative edge-
triggered register to be added to
the DQS enable control path to
satisfy the setup or hold time
requirement for the phase
transfer.
UG-01089
2014.12.17
DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices 47
ALTDQ_DQS2 IP Core User Guide Altera Corporation
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