Altdq_dqs2 data paths, Dq and dqs input path, Dq and dqs input paths for stratix v devices – Altera ALTDQ_DQS2 User Manual
Page 17
Parameter Editor GUI Setting
CLI Parameter
Description
Name
Legal Values
Name
Legal
Values
(1)
Preamble type
high
low
none
PREAMBLE_TYPE
high
low
none
This setting sets the DQS
preamble to high (DDR3),
low (DDR2), or none:
• When you select low
and the strobe is
bidirectional, the
output strobe is held
low for the first full
rate cycle.
• When you select high
or none, the strobe is
driven high for the first
full rate cycle.
• Default value is low.
Note: The ALTDQ_
DQS2 IP core
does not
support DQS
tracking.
Related Information
•
DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices
•
DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices
on page 42
•
ALTDQ_DQS2 Data Paths
Describes the read and write data paths and using other IP cores with the ALTDQ_DQS2 IP core.
DQ and DQS Input Path
The DQ and DQS input paths receive the DQ and DQS signals from the external device during read
operations.
DQ and DQS Input Paths for Stratix V Devices
The following figure shows the input paths where x = 0 to (n-1) and n = the number of DQ pins.
(1)
All CLI parameter values are type string, therefore you must enclose the values in double quotes.
UG-01089
2014.12.17
ALTDQ_DQS2 Data Paths
17
ALTDQ_DQS2 IP Core User Guide
Altera Corporation