Altera ALTDQ_DQS2 - Manual (Page 75)

Example 3: set_multicycle_path Commands
set_multicycle_path -rise_from [get_clocks {virtual_dqs_in}] -rise_to
[get_clocks {dqs_in}] -setup -end 0
set_multicycle_path -fall_from [get_clocks {virtual_dqs_in}] -fall_to
[get_clocks {dqs_in}] -setup -end 0
Constraining Outgoing DQS Strobe
The following commands constraint the outgoing DQS strobe. The design sends the data out by a clock
shifted 270°, so that the non-shifted clock is center-aligned. These constraints specifies that the external
device adds ±150 ps of skew, which could also be described as a setup requirement and hold requirement
of 150 ps. These numbers are an example, and you must modify constraints to reflect data/clock
relationship in their system. Use the
-add
option to add your delay constraint instead of overriding
previous constraints.
Example 4: Constraining DQS Strobe Commands
create_generated_clock -name dqs_out -source [get_pins{pll_inst/alterapll_inst/
altera_pll_i/general[1].gpll � PLL_OUTPUT_COUNTER/divclk}] -phase 0
[get_ports{output_strobe_out}]
set_output_delay -clock { dqs_out } -max 0.150 [get_ports
{read_write_data_io[*]}] -add_delay
set_output_delay -clock { dqs_out } -max 0.150 -clock_fall [get_ports
{read_write_data_io[*]}] -add_delay
set_output_delay -clock { dqs_out } -min -0.150 [get_ports
{read_write_data_io[*]}] -add_delay
set_output_delay -clock { dqs_out } -min -0.150 -clock_fall [get_ports
{read_write_data_io[*]}] -add_delay
UG-01089
2014.12.17
Constraining Outgoing DQS Strobe 75
ALTDQ_DQS2 IP Core User Guide Altera Corporation
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