Altera ALTDQ_DQS2 - Manual (Page 30)

Port Name Type Width
(2)
Description
read_data_out[] Output 2n = full-rate
4n = half-rate
Sends the captured data from the
external device to the core.
This port connects to the output
port of the DDR input register
block ( Figure 8 ). The
read_
data_out[x]
port outputs the
positive-edge triggered data, and
the
read_data_out[n+x]
port
outputs the negative-edge
triggered data.
This port is supported in Arria
V, Cyclone V, and Stratix V
devices.
read_write_data_io[] Bidirec‐
tional
n Receives and sends data between
the core and the external device.
You must assign the bidirec‐
tional DQ port with the output
termination and input termina‐
tion assignments.
This port is supported in Arria
V, Cyclone V, and Stratix V
devices.
write_data_in[] Input 2n = full-rate
4n = half-rate
Receives DDR data signal from
the core to be sent out to the
external device. For example,
data to be written to the external
memory during write operation.
This port connects to the input
port of the half-rate data to
single-rate data output registers
block ( Figure 12 ). In full-rate
mode, the IP core uses only the
write_data_in[x]
and
write_
data_in[n+x]
ports.
This port is supported in Arria
V, Cyclone V, and Stratix V
devices.
(2) The port width applies to full-rate mode, unless otherwise specified.
30 ALTDQ_DQS2 Data Ports
UG-01089
2014.12.17
Altera Corporation ALTDQ_DQS2 IP Core User Guide
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