Altera ALTDQ_DQS2 - Manual (Page 28)

Port Name Type Width Description
strobe_ena_hr_clock_in Input 1 Receives the clock signal from
the clock pin or the PLL to clock
the DQS enable control block.
Also a half-rate signal that, after
going through the
DQS_ENABLE_
CTRL
input, controls the gating of
the input strobe.
This port is supported in Arria
V, Cyclone V, and Stratix V
devices.
strobe_io Bidirectional 1 Sends and receives the bidirec‐
tional clock signal.
This port is supported in Arria
V, Cyclone V, and Stratix V
devices.
strobe_n_io Bidirectional 1 Sends and receives the negative
polarity clock signal for differen‐
tial or complementary strobe
configuration.
This port is supported in Arria
V, Cyclone V, and Stratix V
devices.
output_strobe_out Output 1 Sends clock signal to the external
device. For example, a DQS
signal to the external memory.
This port is supported in Arria
V, Cyclone V, and Stratix V
devices.
output_strobe_n_out Output 1 Sends the negative polarity clock
signal to the external device (For
example, DQSn signal to the
external memory). This port is
available when you set the
output strobe type to differential
or complementary.
This port is supported in Arria
V, Cyclone V, and Stratix V
devices.
28 ALTDQ_DQS2 Data Strobe Ports
UG-01089
2014.12.17
Altera Corporation ALTDQ_DQS2 IP Core User Guide
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