Altera ALTDQ_DQS2 User Manual
Page 100
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Date
Version
Changes
December 2012
2.0
• Updated “ALTDQ_DQS2 Ports” on page 3–
10:
• Major update to Figure 3–8 on page 3–10 to
clearly define the device family support and
the port types.
• Updated Table 3–3 on page 3–8 to include
new ALTDQ_DQS2 data strobe ports and
updated old ALTDQ_DQS2 ports.
• Updated Table 3–5 on page 3–12 to include
new ALTDQ_DQS2 data ports and updated
old ALTDQ_DQS2 data ports.
• Updated Table 3–7 on page 3–14 to update
the description of the ALTDQ_DQS2 PLL
and DLL ports
• Added Table 3–8 on page 3–14 to introduce
the new ALTDQ_DQS2 hard FIFO ports.
• Updated Table 3–9 on page 3–15 to add new
ALTDQ_DQS2 dynamic configuration ports
and to update old ports.
• Added new chapter: “Dynamic Reconfigura‐
tion for ALTDQ_DQS2 Megafunction” on
page 4–1.
• Added new chapter: “Instantiating
Megafunctions” on page 5–1
• Added design examples.
September 2010
1.0
Initial release.
100
Document Revision History
UG-01089
2014.12.17
Altera Corporation
ALTDQ_DQS2 IP Core User Guide
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
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- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
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- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
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