Altera ALTDQ_DQS2 - Manual (Page 32)

ALTDQ_DQS2 Termination Control Ports
Table 8: ALTDQ_DQS2 Termination Control Ports
Port name Type Width Description
parallelterminationcontrol_in[] Input 16 Controls the calibrated
parallel termination ports
of the input buffers.
You must connect this port
to the
paralleltermina-
tioncontrol[15:0]
port
of the ALTOCT IP core.
Ensure that the termination
block located in the
ALTOCT instance is
assigned with the termina‐
tion control block
assignment.
This port is supported in
Arria V, Cyclone V, and
Stratix V devices.
seriesterminationcontrol_in[] Input 16 Controls the calibrated
series termination ports of
the output buffers.
You must connect this port
to the
seriestermina-
tioncontrol[15:0]
port
of the ALTOCT IP core.
Ensure that the termination
block located in the
ALTOCT instance is
assigned with the termina‐
tion control block
assignment.
This port is supported in
Arria V, Cyclone V, and
Stratix V devices.
Related Information
• DC and Switching Characteristics for Stratix V Devices
Describes the dynamic OCT control in Stratix V devices.
32 ALTDQ_DQS2 Termination Control Ports
UG-01089
2014.12.17
Altera Corporation ALTDQ_DQS2 IP Core User Guide
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