Altera ALTDQ_DQS2 - Manual (Page 31)

Port Name Type Width
(2)
Description
write_data_out[] Output n Sends the DDR data signal to the
external device. For example,
data to be written to the external
memory during write operation.
This port connects to the output
port of the output buffer located
between the DDR output
registers block and the DQ-out
pin ( Figure 12 ).
This port is supported in Arria
V, Cyclone V, and Stratix V
devices.
write_oe_in[] Input n = full-rate
2n = half-rate
Receives the gating signal from
the core to control the output
buffer. For example, gating
control when writing data to the
external memory during write
operation.
This port connects to the input
port of the half-rate data to
single-rate data output-enable
registers block ( Figure 12 ). In
full-rate mode, the IP core uses
only the
write_oe_in[x]
port.
This port is supported in Arria
V, Cyclone V, and Stratix V
devices.
Note: To understand how these ports connect to the IOEs, refer to “I/O Elements” in the External
Memory Interfaces in Stratix V Devices chapter of the Stratix V Device Handbook.
(2) The port width applies to full-rate mode, unless otherwise specified.
UG-01089
2014.12.17
ALTDQ_DQS2 Data Ports 31
ALTDQ_DQS2 IP Core User Guide Altera Corporation
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