Altera ALTDQ_DQS2 - Manual (Page 94)

Constraining Outgoing DQS Strobe
The design sends the data out by a clock shifted 270° so that the non-shifted clock is center-aligned. These
constraints state that the external device adds ±250ps of skew, which could also be described as a setup
requirement and hold requirement of 250 ps. These numbers are an example, and you must modify
constraints to reflect the data and clock relationship in the system. Use the
-add
option to add your delay
constraint instead of overriding previous constraints.
Note: Use the
–add
option for the
create_generated_clock
command for the
strobe_io
port because
the port is bidirectional.
The following commands constraint the outgoing DQS strobe.
Example 10: Constraining DQS Strobe Commands
create_generated_clock -name dqs_out -source [get_pins{dqdqs2_inst|
bidir_hardfifo_dqdqs2_inst|altdq_dqs2_inst|phy_clkbuf|outclk[1] }] -phase 0
[get_ports {strobe_io}] -add
set_output_delay -clock {dqs_out} -max 0.250 [get_ports {read_write_data_io[*]}]
-add_delay
set_output_delay -clock { dqs_out } -max 0.250 -clock_fall [get_ports
{read_write_data_io[*]}] - add_delay
set_output_delay -clock {dqs_out} -min -0.250 [get_ports
{read_write_data_io[*]}] -add_delay
set_output_delay -clock { dqs_out } -min -0.250 -clock_fall [get_ports
{read_write_data_io[*]}] - add_delay
Figure 67:
94 Constraining Outgoing DQS Strobe
UG-01089
2014.12.17
Altera Corporation ALTDQ_DQS2 IP Core User Guide
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