Altera ALTDQ_DQS2 - Manual (Page 44)

Legend in I/O Configu‐
ration Block Bit
Sequence for Arria V
GZ and Stratix V
Devices on page 40
Bit Bit Name Description
H 23..18 octdelaysetting2 Connects to the
delayctrlin
port of the second D5 OCT delay
chain.
Controls the dynamic OCT
output register-to-I/O buffer
delay chain (second D5).
For delay values, refer to the
“Programmable IOE Delay”
section in the Stratix V Device
Datasheet .
— 27..24 addrphasesetting
addrpowerdown
addrphaseinvert Unconfigurable bits.
Always set bits to its default
value.
I 29..28 dqsoutputphasesetting Connects to the phasectrlin port
of the clock phase select (in the
DQS output path) to select
between phase shifts of 0°, 45°,
90°, and 135°.
Use this bit to level the DQS
write output.
— 30 dqsoutputpowerdown Unconfigurable bits.
Always set bits to its default
value.
J 31 dqsoutputphaseinvert Connects to the phaseinvertctrl
port of the clock phase select (in
the DQS output path) to select
between the non-inverted and
inverted output.
This setting allows the phase
output from the delay chain to be
inverted to gain additional
phases.
44 DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices
UG-01089
2014.12.17
Altera Corporation ALTDQ_DQS2 IP Core User Guide
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