Altera ALTDQ_DQS2 - Manual (Page 80)

Instantiating Altera PLL
1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.
The parameter editor appears.
2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files
in your project. If prompted, also specify the target Altera device family and output file HDL
preference. Click OK.
3. On the General tab, specify the parameters as shown in the following figures.
Figure 48: Altera PLL Parameter Settings for Arria V Devices
4. Click Finish.
Altera PLL Clock Settings Information
The following table lists the clock settings Information. You may merge the similar frequency counters in
their design, or the Fitter performs the merging automatically.
Table 22: Altera PLL Clock Settings Information
Clock Description
outclk_0 400 MHz. Used as 2x frequency if necessary.
outclk_1 200 MHz. Used as strobe/dqs clock.
outclk_2 200 MHz. 270° phase shifted. Used as data/dq clock.
outclk_3 100 MHz. Used as half-rate clock.
80 Instantiating Altera PLL
UG-01089
2014.12.17
Altera Corporation ALTDQ_DQS2 IP Core User Guide
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