Altera ALTDQ_DQS2 - Manual (Page 46)

Legend in I/O Configu‐
ration Block Bit
Sequence for Arria V
GZ and Stratix V
Devices on page 40
Bit Bit Name Description
N 45 postamblephaseinvert Connects to the phaseinvertctrl
port of the clock phase select (for
the DQS enable control block) to
select between the non-inverted
and inverted output.
Use this clock phase select block
to level the postamble
(dqsenablein signal at the DQS
enable control block).
This setting allows the phase
output from the delay chain to be
inverted to gain additional
phases.
— 65..46 dqs2xoutputphasesetting
n dqs2xoutputpowerdown
dqs2xoutputphaseinvert
dq2xoutputphasesetting
dq2xoutputpowerdown
dq2xoutputphaseinvert
ck2xoutputphasesetting
ck2xoutputpowerdown
ck2xoutputphaseinvert
dqoutputzerophasesetting
postamblezerophasesetting
postamblepowerdown
dividerioehratephaseinvert
dividerphaseinvert Unconfigurable bits.
Always set bits to its default
value.
O 68..66 enaoctcycledelaysetting Connects to the enaoutputcycle‐
delay port of the output
alignment block (in the dynamic
OCT control path) to allow
additional registers to be used.
Use this bit to adjust the phase of
the write-leveled OCT or output
data signal.
46 DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices
UG-01089
2014.12.17
Altera Corporation ALTDQ_DQS2 IP Core User Guide
Send Feedback