Altera ALTDQ_DQS2 - Manual (Page 62)

Figure 23: ALT_OCT Parameter Settings Tab
4. Click Finish.
Instantiating Altera PLL
1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.
The parameter editor appears.
2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files
in your project. If prompted, also specify the target Altera device family and output file HDL
preference. Click OK.
3. On the General tab, specify the parameters as shown in the following figures.
Figure 24: Altera PLL Parameter Settings for Stratix V Devices
4. Click Finish.
Altera PLL Clock Settings Information
The following table lists the clock settings Information. You can either merge the similar frequency
counters in their design, or the Fitter performs the merging automatically.
Table 20: Altera PLL Clock Settings Information
Clock Description
outclk_0 500 MHz, used as 2x frequency if necessary.
outclk_1 250 MHz, used as strobe/dqs clock.
outclk_2 250 MHz, 270 degrees phase shifted. Used as data/dq clock.
62 Instantiating Altera PLL
UG-01089
2014.12.17
Altera Corporation ALTDQ_DQS2 IP Core User Guide
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