Altera ALTDQ_DQS2 - Manual (Page 74)

set_input_delay -clock {virtual_dqs_in} -min -add_delay -0.300
[get_ports{read_write_data_io[*]}]
set_input_delay -clock {virtual_dqs_in} -clock_fall -max -add_delay 0.300 [get_ports
{read_write_data_io[*]}]
set_input_delay -clock {virtual_dqs_in} -clock_fall -min -add_delay -0.300
[get_ports {read_write_data_io[*]}]
Figure 43:
Analyzing Same Edge Transfer
The following
set_false_path
commands ensure that you are analyzing only the same edge transfers, by
removing the opposite edge transfers.
Note: These assignments are optional.
Example 2: set_false_path Commands
set_false_path -setup -rise_from [get_clocks {virtual_dqs_in}] -fall_to
[get_clocks {dqs_in}]
set_false_path -setup -fall_from [get_clocks {virtual_dqs_in}] -rise_to
[get_clocks {dqs_in}]
set_false_path -hold -rise_from [get_clocks {virtual_dqs_in}] -rise_to
[get_clocks {dqs_in}]
set_false_path -hold -fall_from [get_clocks {virtual_dqs_in}] -fall_to
[get_clocks {dqs_in}]
The default setup relationship is to latch data on the next edge. The following
set_multicy-
cles_path
commands direct the TimeQuest Timing Analyzer to analyze the paths as a same-edge
transfer, whereby the same edge that launches data is latched to it. The reason it is latched on the
same edge is that latch edge will be delayed by the DQS circuitry (67.5° in this design example)
into the middle of the data eye.
74 Analyzing Same Edge Transfer
UG-01089
2014.12.17
Altera Corporation ALTDQ_DQS2 IP Core User Guide
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