Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 99)

7-7
Use of the divide-by-0.25 or 0.5 option through the clock divide control bits requires that the crystal multiplier be enabled and the spe-
cific system clock multiply value be established by the 4X/2X bit in the PMR register. The multiplier is enabled by the CTM (PMR.4) bit
but cannot be automatically selected until a startup delay has been established through the CKRY bit in the status register. The 4X/2X
bit can only be altered when the CTM bit is cleared to a logic 0. This prevents the system from changing the multiplier until the system
has moved back to the divide-by-1 mode and the multiplier has been disabled through the CTM bit. The CTM bit can only be altered
when the CD1 and CD0 bits are set to divide-by-1 mode and the RGMD bit is cleared to 0. Setting the CTM to a logic 1 from a previ-
ous logic 0 automatically clears the CKRY bit in the status register and starts the multiplier startup timeout in the multiplier startup
counter. During the multiplier startup period, the CKRY bit remains cleared and the CD1 and CD0 clock controls cannot be set to 00b.
The CTM bit is cleared to a logic 0 on all resets. Figure 7-2 (System Clock Sources) gives a simplified description of the generation of
the system clocks. Specifics of hardware restrictions associated with the use of the 4X/2X, CTM, CKRY, CD1, and CD0 bits are out-
lined in the SFR description.
The microcontroller provides two modes (other than operating) that allow power conservation. They are similar, but have different mer-
its and drawbacks. These modes are idle and stop. In the original 8051, the stop mode is called power-down. These modes are invoked
in the same manner as the original 8051 series.
Idle Mode
Idle mode suspends all CPU processing by holding the program counter in a static state. No program values are fetched and no pro-
cessing occurs. This saves considerable power versus full operation. The virtue of idle mode is that it uses half the power of the oper-
ating state, yet reacts instantly to any interrupt conditions. All clocks remain active so the timers, watchdog, serial port, and power mon-
itor functions are all working. Since all clocks are running, the CPU can exit the idle state using any of the interrupt sources.
Software can invoke the idle mode by setting the IDLE bit in the PCON register at location 87h. The bit is located at PCON.0. The
instruction that executes this step is the last instruction prior to freezing the program counter. Once in idle, all resources are preserved.
There are two ways to exit the idle mode. First, any interrupt (that is enabled) will cause an exit. This results in a jump to the appropri-
ate interrupt vector. The IDLE bit in the PCON register is cleared automatically. Upon returning from this vector using the RETI instruc-
tion, the next address is the one immediately after the instruction that invoked the idle state.
The idle mode can also be removed using a reset. Any of the three reset sources can do this. On receiving the reset stimulus, the CPU
is placed in a reset state and the idle condition cleared. When the reset stimulus is removed, software begins execution as for any
reset. Since all clocks are active, there is no delay after the reset stimulus is removed. Note that if enabled, the watchdog timer con-
tinues to run during idle and must be supported.
Stop Mode
Stop mode is the lowest power state available. This is achieved by stopping all on-chip clocks, resulting in a fully static condition. No
processing is possible, timers are stopped, and no serial communication is possible. Software can invoke stop mode by setting the
STOP bit in the PCON register at location 87h. The bit is located at PCON.1. Processor operation halts on the instruction that sets the
STOP bit. The internal amplifier that excites the external crystal is disabled, halting crystal oscillation in stop mode. Stop mode takes
precedence if application code attempts to set both the STOP and IDLE bits. However, doing this is not suggested. Table 7-1 shows
the state of the processor pins in idle and stop modes.
Stop mode can be exited in two ways. First, like the 8052 microcontrollers, a nonclocked interrupt such as the external interrupts or
the power-fail interrupt can be used. Clocked interrupts, such as the watchdog timer, internal timers, and serial ports do not operate
in stop mode. Note that the bandgap reference must be enabled in order to use the power-fail interrupt to exit stop mode, which
increases stop mode current. Processor operation resumes with the fetching of the interrupt vector associated with the interrupt that
caused the exit from stop mode. When the interrupt service routine is complete, an RETI returns the program to the instruction imme-
diately following the one that invoked the stop mode.
A second method of exiting stop mode is with a reset. The watchdog timer reset is not available as a reset source because no timers
are running in stop mode. An external reset by the RST pin unconditionally exits the device from stop mode. If the BGS bit is set, the
device provides a reset while in stop mode if V
CC
should drop below the VRST level. If the BGS bit is 0, then a dip in power below
V
RST
does not cause a reset. For example, if V
CC
drops to a level of V
RST
-0.5V, then returns to the full level, no reset is generated.
For this reason, use of the bandgap reference is recommended if a brownout condition is possible in stop mode. If power fails com-
pletely (V
CC
= 0V), then a power-on reset is still performed when V
CC
is reapplied, regardless of the state of the BGS bit. Processor
operation resumes execution from address 0000h like any other reset.
Ultra-High-Speed Flash
Microcontroller User’s Guide
Maxim Integrated