Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 148)

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Ultra-High-Speed Flash
Microcontroller User’s Guide
Multiprocessor Communication
The multiprocessor communication mode makes special use of the 9th data bit in modes 2 and 3. In the original 8051, the 9th bit was
restricted to a 0 or 1 condition, but had no special purpose. In the 80C32 and the ultra-high-speed microcontroller, it can be used to
signify that the incoming byte is an address. This allows the processor to be interrupted only if the correct address appears. If the mul-
tiprocessor mode has been enabled, the receive interrupt (signaled by the RI bit) only occurs when a recognized address is received.
When a serial word is received with the 9th bit set and the appropriate SM2 = 1, the byte is assumed to be an address. The address
is compared to an internally stored address. If it matches, a receive interrupt occurs. The internal address is derived from the contents
of two registers. The first register specifies an absolute address. This is the user-specified address of the device. The second register
is a bit-masking register that tells the comparator which address bit(s) to actually use in the comparison. This allows broadcast trans-
missions that reach groups of microcontrollers or all microcontrollers on a serial port. The user defines this protocol.
There are two special function registers that support multiprocessor communication for each UART. These are independent, so that dif-
ferent addresses can be used in each. The registers are SADDR0 or SADDR1 (hex address A9h or AAh) and SADEN0 or SADEN1 (hex
address B9h or BAh). The SADDR register specifies the individual processor’s address. The SADEN identifies address bits that should
be ignored in matching addresses.
Software writes an 8-bit address to the SADDR register. This is the microcontroller’s individual address. Any bit in SADEN that contains
a logic 0 causes the corresponding bit in SADDR to be ignored in comparison. Thus, logic 0 bits in SADEN create “don’t care” bit states
for address comparisons.
When an address is received, each address bit that is not masked by a “don’t care” is compared to the SADDR. The microcontroller
interrupts on any address that matches this comparison. Any address that meets this comparison is called a given address.
The following example shows how one address can be directed to an individual processor, or two out of three:
Micro 1
SADDR 11110000
SADEN 11111010
–––––––––––––––––––––––––
Given 11110x0x
Micro 2
SADDR 11110001
SADEN 11111001
–––––––––––––––––––––––––
Given 11110xx1
Micro 3
SADDR 11110010
SADEN 11111010
–––––––––––––––––––––––––
Given 11110x1x
Note that an address of 11110000 reaches only microcontroller 1. An address of 11110001 reaches both microcontroller 1 and micro-
controller 2. An address of 11110010 reaches only microcontroller 3.
The microcontroller also matches on any address that corresponds to the broadcast address. This is the logical OR of the SADDR and
SADEN registers, with any zeros defined as don’t cares. In most cases, the broadcast address is FFh.
The multiprocessor communication is always enabled. However, the SADEN registers default to 00h, which means all address bits are
“don’t care,” so all match. Thus, if no multiprocessor communication is used, these registers can be ignored.
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