Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 37)

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SM2_1
Bit 5
REN_1
Bit 4
TB8_1
Bit 3
RB8_1
Bit 2
TI_1
Bit 1
RI_1
Multiple CPU Communications. The function of this bit is dependent on the serial port 1 mode.
Mode 0: Selects period for synchronous port 1 data transfers.
Mode 1: When this bit is set, reception is ignored (RI_1 is not set) if invalid stop bit received.
Modes 2/3: When this bit is set, multiprocessor communications are enabled in mode 2 and 3. This
prevents RI_1 from being set, and an interrupt being asserted, if the 9th bit received is not 1.
Receive Enable. This bit enables/disables the serial port 1 receiver shift register.
0 = Serial port 1 reception disabled.
1 = Serial port 1 receiver enabled (modes 1, 2, 3). Initiate synchronous reception (mode 0).
9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial port 1
modes 2 and 3.
9th Received Bit State. This bit identifies the state for the 9th reception bit received data in serial
port 1 modes 2 and 3. In serial port mode 1, when SM2_1 = 0, RB8_1 is the state of the stop bit.
RB8_1 is not used in mode 0.
Transmitter Interrupt Flag. This bit indicates that data in the serial port 1 buffer has been com-
pletely shifted out. In serial port mode 0, TI_1 is set at the end of the 8th data bit. In all other modes,
this bit is set at the end of the last data bit. This bit must be manually cleared by software.
Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Bit 0
port 1 buffer. In serial port mode 1, RI_1 is set at the end of the 8th bit. In serial port mode 1, RI_1
is set after the last sample of the incoming stop bit subject to the state of SM2_1. In modes 2 and
3, RI_1 is set after the last sample of RB8_1. This bit must be manually cleared by software.
SBUF1.7–0
Bits 7–0 Serial Data Buffer 1. Data for serial port 1 is read from or written to this location. The serial trans-
mit and receive buffers are separate registers, but both are addressed at this location.
Bits 7–4
PRAME
Bit 3
These bits are reserved. Read data is 1.
Program RAM Enable. When set (= 1), the internal 1k RAM is mapped as internal program space
between addresses 0400h–07FFh. All program fetches and MOVC accesses are directed to this
1k RAM. When serving as program memory, the RAM continues to be accessible as MOVX data
space (if DME0 = 1). The 1k RAM is not accessible as program space when EA = 0. When clear
(= 0), the internal 1k RAM is not accessible as program space.
R = Unrestricted read, W = Unrestricted write, T = Timed-access write only, -n = Value after reset
ROM Size Select (ROMSIZE)
7 6 5 4 3 2 1 0
SFR C2h — — — — PRAME RMS2 RMS1 RMS0
R-1 R-1 R-1 R-1 RT-0 RT-1 RT-0 RT-1
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Serial Data Buffer 1 (SBUF1)
7 6 5 4 3 2 1 0
SFR C1h SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Ultra-High-Speed Flash
Microcontroller User’s Guide
Maxim Integrated