Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 103)

7-11
Switchback
The switchback feature solves one of the most vexing problems faced by power-conscious systems. Many applications are unable to
use the stop and idle modes because they require constant computation. Traditionally, system designers could not reduce the oper-
ating speed below that required to process the fastest event. This meant that system architects would be forced to operate their sys-
tems at the highest rate of speed, even when it was not required. The switchback feature allows a system to operate at a relatively slow
speed and burst to a faster mode when required by an external event. When this feature is enabled by setting the switchback enable
bit (SWB), (PMR.5), a qualified interrupt, serial port reception, or transmission causes the device to return to the default divide-by-1
mode. A qualified interrupt is defined as an interrupt that has occurred and been acknowledged. This means that an interrupt must be
enabled and also not blocked by a higher priority interrupt. After the event is complete, software can manually return the device to
PMM. The following sources can trigger a switchback:
• External interrupt 0/1/2/3/4/5
• Serial start bit detected, serial port 0/1
• Transmit buffer loaded, serial port 0/1
• Watchdog timer reset
• Power-on reset
• External reset
In the case of a serial port-initiated switchback, the switchback is not generated by the associated interrupt. This is because a device
operating in PMM is not able to correctly receive a byte of data to generate an interrupt. Instead, a switchback is generated by a ser-
ial port reception on the falling edge associated with the start bit, if the associated receiver enable bit (SCON0.4 or SCON1.4) is set.
For serial port transmissions, a switchback is generated when the serial port buffer (SBUF0;99h or SBUF1;C1h) is loaded. This ensures
the device is operating in divide-by-1 mode when the data is transmitted, and eliminates the need for a write to the CD1, CD0 bits to
exit PMM before transmitting. The switchback feature is unaffected by the state of the serial port interrupt flags (RI_0, TI_0, RI_1, TI_1).
The timing of the switchback is dependent on the source. Interrupt-initiated switchbacks occur at the start of the first clock cycle fol-
lowing the event initiating the switchback. In PMM, each internal clock cycle is 1024 external clock cycles. If the current instruction in
progress is a write to the IE, IP, EIE, or EIP registers, interrupt processing is delayed until the completion of the following instruction.
Serial transmit-initiated switchbacks occur at the start of the instruction following the MOV that loads SBUF0 or SBUF1. Serial recep-
tion-initiated switchbacks occur during the cycle in which the falling edge was detected. A few points must be considered when using
a serial port reception to generate a switchback. Under normal circumstances, noise on the line or an aborted transmission causes the
serial port to time out and the data to be ignored. This presents a problem if the switchback is used, however, because a switchback
would occur without indication to the system. If PMM and serial port switchback functions are used in a noisy environment, the user is
advised to periodically check if the device has accidentally exited PMM.
A similar problem can occur if multiprocessor communication protocols are used in conjunction with PMM. The ultra-high-speed flash
microcontroller family supports both the use of the SM2 flag (SCON0.5 or SCON1.5), and the slave address-recognition registers
(SADDR0;A9h, SADDR1;AAh, SADEN0;B9h, SADEN1;BAh) for multiprocessor communications. The problem is that an invalid address,
which should be ignored by a particular processor, still generates a switchback. As a result, it is not recommended to use a multi-
processor communication scheme in conjunction with PMM. If the system power considerations allow for an occasional erroneous
switchback, a polling scheme can be used to place the device back into PMM.
Ultra-High-Speed Flash
Microcontroller User’s Guide
Maxim Integrated