Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 106)

8-2
Ultra-High-Speed Flash
Microcontroller User’s Guide
SECTION 8: RESET CONDITIONS
The condition that causes the microcontroller to vector to address 0000h is a reset. This can happen internally or external to the micro-
controller. The reset condition puts the microcontroller in a known state following a course of events not anticipated by the designer.
The circuit could be subjected to numerous conditions, such as power brownout, noise due to lightning strike, or corrupted code.
Reset Sources
The microcontroller can enter a reset condition if invoked in one of five ways:
• Power-on/power-fail reset
• Watchdog timer reset
• Oscillator-fail detect reset
• External reset
The reset state is the same, regardless of the source of the reset. When in reset, the oscillator is running, but no program execution is
allowed. When the reset source is external, the user must remove the reset stimulus to continue operation. When power is applied to
the device, the power-on delay removes the stimulus automatically.
Power-On/Power-Fail Reset
The ultra-high-speed flash microcontroller incorporates an internal voltage reference, which holds the device in power-on reset while
V
CC
is out of tolerance. Once V
CC
has risen above the threshold, the device restarts the external crystal oscillator and counts 65,536
clock cycles before program execution begins at location 0000h. The power monitor invokes a reset state when V
CC
drops below the
threshold condition. The condition remains in effect while power is below the minimum voltage level. When power returns above the
reset threshold, a full power-on reset is performed. This mechanism provides a controlled and predictable startup condition.
The processor exits the reset condition automatically once V CC meets the minimum voltage requirement. This helps the system main-
tain reliable operation by only permitting processor operation when voltage is in a known good state. Software can determine that a
power-on reset has occurred by checking the power-on reset flag (POR) in the WDCON register. Software should clear the POR bit
after it is read.
Watchdog Timer Reset
The ultra-high-speed flash microcontroller incorporates a safety feature to prevent corrupted software from controlling the CPU. This
feature is called the watchdog timer. It is a free-running timer with a programmable interval. The watchdog supervises the processor
operation by requiring software to clear the timer before an overflow occurs. If the timer is enabled and software fails to clear it before
this interval expires, the ultra-high-speed flash microcontroller is placed into a reset state. The reset state maintains for 13 clock cycles.
Once the reset is removed, the processor resumes execution at address 0000h. Software can determine if a reset is caused by a watch-
dog timeout by checking the watchdog timer reset flag (WTRF) in the WDCON register. This flag is cleared by software only.
Oscillator Fail-Detect Reset
Oscillator fail-detect circuitry monitors the on-chip oscillator activity. When enabled, this circuit causes a reset if the oscillator frequen-
cy falls below ~20kHz, and holds the chip in reset until the oscillator frequency rises back above ~20kHz. The circuitry is enabled by
setting the OFDE (PCON.4) bit to a logic 1. The OFDE bit can be cleared by software or by the occurrence of a power-fail reset. A reset
caused by an oscillator failure sets the OFDF (PCON.5) flag bit to a logic 1. This flag can be cleared by software or by a power-on
reset. The oscillator fail-detect circuitry utilizes the internal ring oscillator to clock the chip into the reset state and maintain the reset
state while the oscillator is below the minimum frequency. Note, however, that the circuitry does not force a reset when the oscillator is
purposely stopped when software invokes stop mode.
Maxim Integrated