Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 113)

9-6
Ultra-High-Speed Flash
Microcontroller User’s Guide
Interrupt Latency
Interrupt response time is normally between 4 and 18 memory cycles, depending on the state of the microcontroller when the interrupt
occurs. If the microcontroller is performing an ISR with equal or greater priority, interrupt latency increases because the new interrupt
is not invoked. In other cases, the response time depends on the current instruction. The fastest possible response to an interrupt is
four memory cycles. The four memory cycle response time includes one cycle for detecting the interrupt and three cycles to perform
the LCALL that is inherent in the interrupt request.
The maximum response time occurs if the microcontroller is performing a JBC instruction that clears a bit in IE, IP0, EIE, or EIP0, and
then executes a DIV as the next instruction. From the time an interrupt source is activated (not detected), the longest reaction time is
18 memory cycles. This includes one cycle to detect the interrupt, four cycles to finish the JBC, ten cycles to perform the DIV, then
three cycles for the LCALL to the ISR. This maximum response time of eighteen memory cycles assumes that there are no other pend-
ing interrupts of higher priority to be serviced and that the JBC instruction is not preceded and does not jump to any instruction that
aborts the priority decoding process (RETI or writes to IP0, IP1, EIP0, EIP1, IE, or EIE).
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