External reset, Determining the cause of a r, External reset -3 – Maxim Integrated Ultra-High-Speed Flash Microcontroller User Manual
Page 107: Determining the cause of a reset -3, Table 8-1. reset source flag associations -3, Determining the cause of a reset, Table 8-1. reset source flag associations

8-3
External Reset
If the RST input is asserted to logic 1, the device is forced into a reset state. An external reset is accomplished by holding the RST pin
high at least four clock cycles while the oscillator is running. Once the reset state is invoked, it is maintained as long as RST is assert-
ed at logic 1. When the RST is removed, the processor exits the reset state within four clock cycles and begins execution at address
0000h.
If an RST is applied while the processor is in the stop mode, the RST causes the oscillator to begin running and forces the program
counter to 0000h. The reset delay is 65,536 clock cycles to allow the oscillator to stabilize.
The RST pin is a bidirectional I/O. If a reset is caused by a power fail reset, a watchdog timer reset, an oscillator fail detect reset, or
an internal system reset, a positive output level is also generated at the RST pin. This reset level is asserted as long as an internal reset
is asserted. The drive capability of this I/O port may be insufficient if the RST pin is connected to a RC reset circuit. Connecting the
RST pin to a capacitor would not affect the internal reset condition.
Determining The Cause Of a Reset
During the debugging process, it might be necessary to isolate the cause of a device reset. Because resets are initiated by a limited
number of sources, it is relatively easy to determine their source by interrogating the flag bits associated with the reset sources. The
table below lists the reset sources and flag bits. Although no flag bits are associated with the internal system reset generated by issu-
ing a system reset or complement bank-select flash command, it is unlikely that these would occur unintentionally, given that the flash
command bits (FCNTL.3-0) require a timed-access write.
Table 8-1. Reset Source Flag Associations
RESET SOURCE
FLAG BIT
Power-on reset
POR – WDCON.6
Watchdog reset
WTRF – WDCON.2
Oscillator fail-detect reset
OFDF – PCON.5
Internal system reset
None
External reset
None
Ultra-High-Speed Flash
Microcontroller User’s Guide
Maxim Integrated