Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 132)

11-12
Ultra-High-Speed Flash
Microcontroller User’s Guide
Watchdog Timer
The watchdog timer reset provides CPU monitoring by requiring software to clear the timer before the user-selected interval expires. If
the timer is not reset, the CPU can be reset by the watchdog. The watchdog function is optional and is described below.
The watchdog timer is a user-programmable clock counter that can serve as a time-base generator, an event timer, or a system super-
visor. As can be seen in Figure 11-9, the timer is driven by the main system clock that is supplied to a series of dividers. The divider
output is selectable, and determines the interval between timeouts. When the timeout is reached, an interrupt flag is set, and if enabled,
a reset occurs. The interrupt flag causes an interrupt to occur if its individual enable bit is set and the global interrupt enable is set.
The reset and interrupt are completely discrete functions that may be acknowledged or ignored, together or separately for various
applications.
The watchdog timer reset function works as follows. After initializing the correct timeout interval (discussed later), software first restarts
the watchdog using RWT (WDCON.0) and then enables, if desired, the reset function by setting the enable watchdog timer reset (EWT
= WDCON.1) bit. Any time prior to reaching its user-selected terminal value, software can set the reset watchdog timer (RWT =
WDCON.0) bit. If the watchdog timer is reset (RWT bit written to a logic 1) before the timeout period expires, the timer starts over.
Hardware automatically clears the RWT after software sets it.
If the timeout is reached without RWT being set, hardware generates a watchdog interrupt if the interrupt source has been enabled. If
no further action is taken to prevent a watchdog reset in the 512 system clock cycles following the timeout, hardware has the ability to
reset the CPU if EWT = 1. When the reset occurs, the watchdog timer reset flag (WTRF = WDCON.2) is automatically set to indicate
the cause of the reset; however, software must clear this bit manually.
The watchdog timer is a free-running timer. When used as a simple timer with both the reset and interrupt functions disabled (EWT =
0 and EWDI = 0), the timer continues to set the watchdog interrupt flag each time the timer completes the selected timer interval as
programmed by WD1 (CKCON.7) and WD0 (CKCON.6). Restarting the timer using the RWT (WDCON.0) bit allows software to use the
timer in a polled timeout mode. The WDIF bit is cleared by software or any reset.
TIMERS 0, 1, 2
INPUT CLOCK FREQUENCY SYSTEM CLOCK MODE
PMR REGISTER BITS
4X/2X, CD1, CD0
TxMH,TxM = 00 TxMH,TxM = 01 TxMH,TxM = 1x
Crystal multiply mode 4X 100 OSC / 12 OSC / 1 OSC / 0.25
Crystal multiply mode 2X 000 OSC / 12 OSC / 2 OSC / 0.5
Divide-by-1 (default) X01, X10 OSC / 12 OSC / 4 OSC / 1
Power-management mode
(divide-by-1024)
X11 OSC / 3072 OSC / 1024 OSC / 1024
Table 11-2. Timers 0, 1, 2 Input Clock Frequency
SYSTEM CLOCK MODE
PMR REGISTER BITS
4X/2X, CD1, CD0
TIMER 2
BAUD-RATE GENERATION/CLOCK OUTPUT MODE
INPUT CLOCK FREQUENCY (TxMH, TxM = xx)
Crystal multiply mode 4X 100 OSC / 2
Crystal multiply mode 2X 000 OSC / 2
Divide-by-1 (default) X01, X10 OSC / 2
Power management mode
(divide-by-1024)
X11 OSC / 2048
Table 11-3. Timer 2 Baud-Rate Generation/Clock Output Mode
Maxim Integrated