Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 53)

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Ultra-High-Speed Flash
Microcontroller User’s Guide
2-Byte Instructions
All 2-byte instructions require a minimum of two cycles, since fetching each byte requires a separate memory access. The first byte is
the instruction op code that is decoded by the CPU. The second byte is normally an operand, or it can specify the location of the
operand. For example, “ADD A, direct” is a 2-byte, two-cycle instruction where the second byte specifies the direct address location
of the operand. Due to internal access restrictions, certain direct addressing instructions require one extra memory cycle when oper-
ating on the PSW, SP, DPS, IE, EIE, IP0, IP1, EIP0, or EIP1 register. Following are examples of these and other 2-byte instructions:
OPCODE OPERAND/LOCATION NO. OF CYCLES
ADD A, direct 25h 2
ADD A, #data 24h 2
SJMP rel 80h 3
ANL direct, A 52h 2 or 3
ORL direct, A 42h 2 or 3
DJNZ Rn, direct D8h-DFh 4
3-Byte Instructions
Three-byte instructions require a minimum of three cycles since each byte fetch requires one memory cycle. The first byte, the opcode,
instructs the CPU on how to handle the next two bytes. Most 3-byte instructions involve comparison or branching, but not all. Just like
the 2-byte instructions, certain 3-byte instructions may require 1 extra memory cycle when operating on the PSW, SP, DPS, IE, EIE, IP0,
IP1, EIP0, or EIP1 register. Following are examples of 3-byte instructions.
OPCODE OPERAND(s)/LOCATION(s) NO. Of CYCLES
LJMP addr16 02h 3
MOV dptr, #data16 90h 3
MOV direct, direct 85h 3 or 4
JBC bit, rel 10h 4 or 5
DJNZ direct, rel D5h 5
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