Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 142)

12-8
Ultra-High-Speed Flash
Microcontroller User’s Guide
Serial I/O Description
A detailed description and block diagram of each serial mode follow. Note that the baud clock input (to the serial I/O control block)
corresponding to the power-management mode has been omitted from each of the block diagrams. Reference the tables earlier in this
section for power-management mode baud clock rates. A description of framing-error detection and multiprocessor communication
follows this section.
Mode 0
Mode 0 is used to communicate in synchronous, half-duplex format with devices that accept the ultra-high-speed microcontroller as a
master. Figure 12-1 shows a functional block diagram and basic timing of this mode. As can be seen, there is one bidirectional data
line (RXD) and one shift clock line (TXD) used for communication. The shift clock is used to shift data into and out of the microcon-
troller and the remote device. Mode 0 requires that the microcontroller is the master, because the microcontroller generates the serial
shift clocks for both directions. As described above, the shift clock can be selected to be either divide by 12 or divide by 4 of the sys-
tem clock (not oscillator) as determined by the SM2 (SCON0.5 or SCON1.5) bit.
The RXD signal is used for both transmission and reception. TXD provides the shift clock. Data bits enter and exit least-significant bit
(LSb) first. The baud rate is equal to the shift clock frequency. The relevant UART begins transmitting when any instruction writes to
SBUF0 or SBUF1 (address 99h or C1h). The internal shift register then begins to shift data out. The clock is activated and transfers
data until the 8-bit value is complete. Data is presented just prior to the falling edge of the shift clock (TXD) so that an external device
can latch the data using the rising edge.
The UART begins to receive data when the REN bit in the SCON register (SCON0.4 or SCON1.4) is set to a logic 1 and the RI bit
(SCON0.0 or SCON1.0) is set to a logic 0. This condition tells the UART that there is data to be shifted in. The shift clock (TXD) acti-
vates, and the UART latches incoming data on the rising edge. The external device should therefore present data on the falling edge.
This process continues until 8 bits have been received. The RI bit is automatically set to a logic 1 immediately following the last rising
edge of the shift clock on TXD. This causes reception to stop until the SBUF has been read, and the RI bit cleared. When RI is cleared,
another byte can be shifted in.
Mode 1
Mode 1 is asynchronous and full duplex, using a total of 10 bits. The 10 bits consist of a start bit (logic 0), 8 data bits, and 1 stop bit
(logic 1) as illustrated in Figure 12-2. The data is transferred LSb first. As described above, the baud rates for mode 1 are generated
by either a divide-by-16 of timer 1 rollover, a divide-by-16 of the timer 2 rollover, or a divide-by-32 of timer 1 rollover. The UART begins
transmission after the first rollover of the divide-by-16 counter following a software write to SBUF. Transmission takes place on the TXD
pin. It begins by the start bit being placed on the pin. Data is then shifted out onto the pin, LSb first. The stop bit follows. The TI bit is
set by hardware after the stop bit is placed on the pin. All bits are shifted out at the rate determined by the baud-rate generator.
Once the baud-rate generator is active, reception can begin at any time. The REN bit (SCON0.4 or SCON1.4) must be set to a logic 1
to allow reception. The falling edge of a start bit on the RXD pin begins the reception process. Data is shifted in at the selected baud
rate. At the middle of the stop bit time, certain conditions must be met to load SBUF with the received data:
• RI must = 0, and either
• If SM2 = 0, the state of the stop bit does not matter, or
• If SM2 = 1, the state of the stop bit must = 1.
If these conditions are true, then SBUF (hex address 99h or C1h) is loaded with the received byte, the RB8 bit (SCON0.2 or SCON1.2)
is loaded with the stop bit, and the RI bit (SCON0.0 or SCON1.0) is set. If these conditions are false, then the received data is lost
(SBUF and RB8 not loaded) and RI is not set. Regardless of the receive word status, after the middle of the stop bit time, the receiver
goes back to looking for a 1 to 0 transition on the RXD pin.
Each data bit received is sampled on the 7th, 8th, and 9th clock used by the divide-by-16 counter. Using majority voting, two equal
samples out of the three determine the logic level for each received bit. If the start bit was determined to be invalid ( = 1), then the
receiver goes back to looking for a 1 to 0 transition on the RXD pin in order to start the reception of data.
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