Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 78)

6-11
Page Mode 2 Bus Structure
The page mode 2 external bus structure multiplexes the most significant address byte with data on P2 and uses P0 for the least sig-
nificant address byte. An illustration of this memory interface is provided in Figure 6-6.
This bus structure speeds up external code fetches only. Aside from the different functions of P0 and P2 when operating in page mode
2, the external memory accesses are equal in duration and timing to those made in the nonpage mode. Figure 6-7 illustrates memory
cycles for the page mode 2 bus structure.
Internal Memory Cycles
C2 C3 C4 C1 C2 C1 C2
XTAL1
ALE
Port 0
Port 2
PSEN
C1
Ext Code Fetches
Page Miss Page Hit Page Hit
Data Data
LSB Add LSB Add LSB Add
Data MSB Add
Figure 6-7. Page Mode 2 External Code Fetch Cycle (CD1:0 = 10b)
PSEN
ALE CK
74F373
LATCH
MSB ADDRESS
DATA BUS
LSB ADDRESS
PORT 0
(8)
(8)
64kB X 8
MEMORY
(8)
OE
CE
PORT 2
DS89C4x0
Figure 6-6. Program Memory Interconnect (Page Mode 2)
Ultra-High-Speed Flash
Microcontroller User’s Guide
Maxim Integrated