Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 118)

10-5
XTAL1
ALE
PORT 0
PORT 2
PSEN
C1 C2 C3 C4 C1 C2 C1 C2
EXT CODE FETCHES
PAGE MISS
INTERNAL MEMORY CYCLES
PAGE HIT PAGE HIT
MSB ADD
LSB ADD LSB ADD LSB ADD
DATA DATA DATA
Figure 10-5. External Program Memory Access (Page Mode 2)
ALE
PSEN
Port 0
Port 2
ALE
PSEN
Port 0
Port 2
RD / WR
XTAL1
Inst Inst Inst Inst Inst
MSB LSB LSB LSB LSB LSB LSB LSB
Inst
Data
Memory Access (Stretch = 4)
MOVX Instruction (Page miss)
1st
Cycle
2nd
Cycle
3rd
Cycle
4th
Cycle
9th
Cycle
MOVX
Instruction
Fetch
LSB LSB LSB
Inst Inst Inst
MOVX Instruction (Page hit)
Memory Access (Stretch = 4)
MOVX
Instruction
Fetch
1st
Cycle
2nd
Cycle
3rd
Cycle
4th
Cycle
5th
Cycle
9th
Cycle
LSB LSB LSB LSB
Inst Inst Inst Inst
RD / WR
Data
LSB
Figure 10-4. External Program Memory Access (Page Mode 1)
Ultra-High-Speed Flash
Microcontroller User’s Guide
Maxim Integrated