Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 29)

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CKRY
Bit 3
RGMD
Bit 2
RGSL
Bit 1
BGS
Bit 0
Clock Ready. This bit indicates the status of the startup period for the crystal oscillator or crystal
multiplier warm-up period. This bit is cleared after a reset or when exiting STOP mode. It is also
cleared when the clock multiplier is enabled (setting of PMR.4 = 1). Once CKRY is cleared, a
65,536 clock count must take place before CKRY is set and the lockout preventing modification of
CD1:CD0 is removed. Once CKRY is set (= 1), the clock multiplier can then be selected as the
clock source or switchover from the ring oscillator to the crystal oscillator can occur.
Ring Mode Status. This status bit indicates the current clock source for the device. This bit is
cleared to 0 after a power-on reset and unchanged by all other forms of reset.
0 = Device is operating from the external crystal or oscillator.
1 = Device is operating from the ring oscillator.
Ring Oscillator Select. When set (= 1), this bit enables operation using the on-chip ring oscillator
as the clock source until the oscillator warm-up period has completed (CKRY = 1). Using the ring
oscillator to resume from stop mode allows almost instantaneous startup. This bit is cleared to 0
after a power-on reset and unchanged by all other forms of reset.
0 = Device operation is held until completion of the crystal oscillator warm-up delay period.
1 = The device begins operating from the ring oscillator and switch over to the crystal oscillator
upon completion of the warm-up delay period.
Bandgap Select. This bit enables/disables the bandgap reference during stop mode. Disabling
the bandgap reference provides significant power savings in stop mode but sacrifices the ability
to perform a power-fail interrupt or power-fail reset while stopped. This bit can only be modified with
a timed access procedure.
0 = The bandgap reference is disabled in stop mode but functions during normal operation.
1 = The bandgap reference operates in stop mode.
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Timer and Serial Port Clock Mode Register (CKMOD)
7 6 5 4 3 2 1 0
SFR 96h — — T2MH T1MH T0MH — — —
RW-1 RW-1 RW-0 RW-0 RW-0 RW-1 RW-1 RW-1
Bits 7, 6
T2MH
Bit 5
T1MH
Bit 4
T0MH
Bit 3
Bits 2–0
Reserved.
Timer 2 Clock Mode High-Speed Select. When set (= 1), the system clock is used as the input
clock for Timer 2, and the T2M bit (CKCON.5) setting is ignored. When clear (= 0), the input clock
for Timer 2 is selected using the T2M bit.
Timer 1 Clock Mode High-Speed Select. When set (= 1), the system clock is used as the input
clock for Timer 1, and the T1M bit (CKCON.4) setting is ignored. When clear (= 0), the input clock
for Timer 1 is selected using the T1M bit.
Timer 0 Clock Mode High-Speed Select. When set (= 1), the system clock is used as the input
clock for Timer 0, and the T0M bit (CKCON.3) setting is ignored. When clear (= 0), the input clock
for Timer 0 is selected using the T0M bit.
Reserved. Read data is 1.
Ultra-High-Speed Flash
Microcontroller User’s Guide
Maxim Integrated