Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 145)

12-11
Ultra-High-Speed Flash
Microcontroller User’s Guide
Mode 2
Mode 2 uses a total of 11 bits in asynchronous full-duplex communication, as illustrated in Figure 12-3. The 11 bits consist of 1 start
bit (a logic 0), 8 data bits, 1 programmable 9th bit, and one stop bit (a logic 1). Like mode 1, the transmissions occur on the TXD sig-
nal pin and receptions on RXD. For transmission purposes, the 9th bit can be stuffed as a logic 0 or 1. A common use is to put the par-
ity bit in this location. The 9th bit is transferred from the TB8 bit position in the SCON register (SCON0.3 or SCON1.3) during the write
to SBUF. Baud rates are generated as a fixed function of the crystal frequency, as described earlier in this section. Like mode 1, mode
2’s transmission begins after the first rollover of the divide-by-16 counter following a software write to SBUF. It begins by the start bit
being placed on the TXD pin. The data is then shifted out onto the pin LSb first, followed by the 9th bit, and finally the stop bit. The TI
bit (SCON0.1 or SCON1.1) is set when the stop bit is placed on the pin.
Reception begins when a falling edge is detected as part of the incoming start bit on the RXD pin. The RXD pin is then sampled accord-
ing to the baud-rate speed. The 9th bit is placed in the RB8 bit location in SCON (SCON0.2 or SCON1.2). When a stop bit has been
received, the data value is transferred to the SBUF receive register (hex address 99 or C1). The RI bit (SCON0.0 or SCON1.0) is set to
indicate that a byte has been received. At this time, the UART can receive another byte.
Once the baud-rate generator is active, reception can begin at any time. The REN bit (SCON0.4 or SCON1.4) must be set to a logic 1
to allow reception. The falling edge of a start bit on the RXD pin begins the reception process. Data must be shifted in at the selected
baud rate. At the middle of the 9th bit time, certain conditions must be met to load SBUF with the received data.
• RI must = 0, and either
• If SM2 = 0, the state of the 9th bit does not matter, or
• If SM2 = 1, the state of the 9th bit must = 1.
If these conditions are true, then SBUF is loaded with the received byte, RB8 is loaded with the 9th bit, and RI is set. If these condi-
tions are false, then the received data is lost (SBUF and RB8 not loaded) and RI is set. Regardless of the receive word status, after the
middle of the stop bit time, the receiver goes back to looking for a 1 to 0 transition on RXD.
Data is sampled in a similar fashion to mode 1 with the majority voting on three consecutive samples. Mode 2 uses the sample divide-
by-16 counter with either the oscillator divided by 2 or 4.
Mode 3
Mode 3 has the same operation as mode 2, except for the baud-rate source. As shown in Figure 12-4, mode 3 can use timer 1 or 2 for
serial port 0 and timer 1 for serial port 1. The bit shifting and protocol are the same.
Framing Error Detection
A framing error occurs when a valid stop bit is not detected. This results in the possible improper reception of the serial word. The
UART can detect a framing error and notify the software. Typical causes of framing errors are noise and contention. The framing error
condition is reported in the SCON register for the corresponding UART.
The framing error bit, FE, is located in SCON0.7 or SCON1.7. Note that this bit normally serves as SM0 and is described as SM0/FE_0
or SM0/FE_1 in the register description. Framing error information is made accessible by the SMOD0 framing error detection enable
bit located at PCON.6. When SMOD0 is set to a logic 1, the framing error information is shown in SM0/FE (SCON0.7 or SCON1.7).
When SMOD0 is set to a logic 0, the SM0 function is accessible. The information for bits SM0 and FE is actually stored in different reg-
isters. Changing SMOD0 only modifies which register is accessed; not the contents of either.
The FE bit is set to a 1 when a framing error occurs. It must be cleared by software. Note that the SMOD0 state must be 1 while read-
ing or writing the FE bit. Also note that receiving a properly framed serial word does not clear the FE bit. This must be done in software.
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