Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 45)

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RWT
Bit 0 Reset Watchdog Timer. Setting this bit resets the watchdog timer count. This bit must be set using
a Timed Access procedure before the watchdog timer expires, or a watchdog timer reset and/or
interrupt is generated if enabled. The timeout period is defined by the Watchdog Timer Mode
Select bits (CKCON.7-6). This bit is always 0 when read.
ACC.7–0
Bits 7–0 Accumulator. This register serves as the accumulator for arithmetic operations.
Bits 7–5
EWDI
Bit 4
EX5
Bit 3
EX4
Bit 2
EX3
Bit 1
EX2
Bit 0
Reserved. Read data is 1.
Watchdog Interrupt Enable. This bit enables/disables the watchdog interrupt.
0 = Disable the watchdog interrupt.
1 = Enable interrupt requests generated by the watchdog timer.
External Interrupt 5 Enable. This bit enables/disables external interrupt 5.
0 = Disable external interrupt 5.
1 = Enable interrupt requests generated by the INT5 pin.
External Interrupt 4 Enable. This bit enables/disables external interrupt 4.
0 = Disable external interrupt 4.
1 = Enable interrupt requests generated by the INT4 pin.
External Interrupt 3 Enable. This bit enables/disables external interrupt 3.
0 = Disable external interrupt 3.
1 = Enable interrupt requests generated by the INT3 pin.
External Interrupt 2 Enable. This bit enables/disables external interrupt 2.
0 = Disable external interrupt 2.
1 = Enable interrupt requests generated by the INT2 pin.
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Extended Interrupt Enable (EIE)
7 6 5 4 3 2 1 0
SFR E8h — — — EWDI EX5 EX4 EX3 EX2
R-1 R-1 R-1 RW-0 RW-0 RW-0 RW-0 RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Accumulator (A or ACC)
7 6 5 4 3 2 1 0
SFR E0h ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Ultra-High-Speed Flash
Microcontroller User’s Guide
Maxim Integrated