Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 73)

6-6
Ultra-High-Speed Flash
Microcontroller User’s Guide
Internal SRAM Memory
The ultra-high-speed microcontroller incorporates an internal 1kB SRAM that is usable as data, program, or merged program/data mem-
ory. Upon a power-on reset, the internal 1kB memory is disabled and transparent to both program and data memory maps.
When used for data, the memory is addressed through MOVX commands, and is in addition to the 256 bytes of scratchpad memory.
To enable the 1kB SRAM as internal data memory, software must set the DME0 bit (PMR.0). After setting this bit, all MOVX accesses
within the first 1kB (0000h–03FFh) are directed to the internal SRAM. Any data memory accesses outside of this range are still direct-
ed to the expanded bus. One advantage of using the internal data memory is that MOVX operations automatically default to the fastest
access possible. Note that the DME0 bit is cleared after any reset, so access to the internal data memory is prohibited until this bit is
modified. The contents of the internal data memory are not affected by the changing of the data memory enable (DME0) bit.
Table 6-2 shows how the DME1, DME0 bits affect the data memory map.
Table 6-2. Data Memory Access Control
When configured as program memory, code fetches and MOVC read operations can be directed to this 1kB internal SRAM. To enable
the 1kB SRAM as internal program memory, software must set the PRAME bit (ROMSIZE.3). After setting this bit, code accesses to the
address range 0400h–07FFh are made to the internal 1kB SRAM in place of the program memory previously mapped to that address
range. For applications using only external program memory (EA = 0), the internal 1kB SRAM cannot be enabled as program space.
The internal 1kB SRAM can serve as merged program/data memory if both the DME0 and PRAME bits have been set. This feature can
be effective for changing small pieces of frequently executed code, but be cautious when employing self-modifying code techniques.
Program Memory Interface—Nonpage Mode
The ultra-high-speed flash microcontroller defaults to a nonpage mode, external program memory interface. This memory interconnect
scheme is the same as is used for the high-speed microcontroller family, and is shown in Figure 6-2. This example uses the DS89C420
and one 64k x 8 memory device. The program store enable (PSEN) signal is used to provide an output enable to the memory. It can
also be used to provide a chip enable, but this generally results in less-favorable timing. The address LSB and data are multiplexed
on port 0, and the address MSB is provided on port 2. An external latch, shown in the diagram as a 74F373, is used to latch the lower
byte of the address to the memory device. The address latch enable (ALE) signal controls the timing of the latch so that the operation
is performed in the proper sequence. The signals and relative timing for a program access are shown in Figure 6-3.
When implementing a high-speed memory interface, the F series (or faster) logic should be used. HC logic has worst-case propaga-
tion delays that are too long. Specifications for all devices should be checked. More information on the nonpage mode memory inter-
face timing can be found in Application Note 57 (DS80C320 Memory Interface Timing) and Application Note 85 (High-Speed
Microcontroller Interface Timing).
The DS89C420 provides an extremely high-speed interface to external memory. This allows for use of the slowest, and least expen-
sive, memory device for a given crystal speed. The ultra-high-speed flash microcontroller provides very fast slew rates to allow the
maximum possible time for memory access. Refer to the electrical specifications for exact timing.
DME1 DME0 DATA MEMORY ADDRESS RANGE DATA MEMORY LOCATION
0 0 0000h–FFFFh External Data Memory (default)
X 1
0000h–03FFh
0400h–FFFFh
Internal Data Memory
External Data Memory
1 0 Reserved Reserved
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