beautypg.com

Maxim Integrated Ultra-High-Speed Flash Microcontroller User Manual

Page 92

background image

6-25

; THIS LOOP IS PERFORMED R5 TIMES, IN THIS EXAMPLE 64

MOVX

A, @DPTR

; READ SOURCE DATA BYTE

3 +D

INC

DPS

; CHANGE DPTR TO DESTINATION

4 +C

MOVX

@DPTR, A

; WRITE DATA TO DESTINATION

3 +D

INC

DPS

; CHANGE DATA POINTER TO SOURCE

4 +C

DJNZ

R5, MOVE

; FINISHED WITH TABLE?

4

ANL

DPS, #0EFH

; CLEAR AUTO-INC/DEC

3

PROGRAM 4: 64-BYTE BLOCK MOVE (DUAL DATA POINTER, TSL)

; SH and SL are high and low byte source address.

; DH and DL are high and low byte of destination address.

; DPS is the data pointer select. Reset condition DPTR0.

# UHSM CYCLES

DPS

EQU 86h

; TELL ASSEMBLER ABOUT DPS

MOV

R5, #64

; NUMBER OF BYTES TO MOVE

2

ORL

DPS, #20h

; SET TOGGLE SELECT (TSL)

3

MOV

DPTR, #SHSL

; LOAD SOURCE ADDRESS

3

MOV

DPTR, #DHDL

; LOAD DESTINATION ADDRESS

3

MOVE:

; THIS LOOP IS PERFORMED R5 TIMES, IN THIS EXAMPLE 64

MOVX

A, @DPTR

; READ SOURCE DATA BYTE

3 +D

MOVX

@DPTR, A

; WRITE DATA TO DESTINATION

4 +CD

INC

DPTR

; NEXT SOURCE ADDRESS

2 +C

INC

DPTR

; NEXT DESTINATION ADDRESS

1

DJNZ

R5, MOVE

; FINISHED WITH TABLE?

4

ANL

DPS, #0DFh

; CLEAR TOGGLE SELECT

3

PROGRAM 5: 64-BYTE BLOCK MOVE (DUAL DATA POINTER, AID, TSL)

; SH and SL are high and low byte source address.

; DH and DL are high and low byte of destination address.

; DPS is the data pointer select. Reset condition DPTR0.

# UHSM CYCLES

DPS

EQU 86h

; TELL ASSEMBLER ABOUT DPS

MOV

R5, #64

; NUMBER OF BYTES TO MOVE

2

ORL

DPS, #30h

; SET TOGGLE SELECT, AUTO-INC/DEC

3

MOV

DPTR, #SHSL

; LOAD SOURCE ADDRESS

3

MOV

DPTR, #DHDL

; LOAD DESTINATION ADDRESS

3

MOVE:

; THIS LOOP IS PERFORMED R5 TIMES, IN THIS EXAMPLE 64

MOVX

A, @DPTR

; READ SOURCE DATA BYTE

3 +D

MOVX

@DPTR, A

; WRITE DATA TO DESTINATION

4 +CD

DJNZ

R5, MOVE

; FINISHED WITH TABLE?

5 +C

ANL

DPS, #0CFh

; CLEAR TSL, AID

3

Note that since each pass through the loop saves additional clock cycles when compared to the single DPTR approach, efficiency

improvement when moving larger blocks is even greater using these features. Further speed improvement can be gained when exe-

cuting from internal flash program memory, since no code-fetch page misses (+C) would occur. For example, running Program 5 from

internal memory at 33MHz would require only 19.8µs (= 1/33MHz x (14 + 64 x 10)).

Ultra-High-Speed Flash
Microcontroller User’s Guide

Maxim Integrated