Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 58)

5-11
Page Mode 1 External Timing—Pages 1:0 = 10b (Four Cycles) (continued)
Figure 5-13 and Figure 5-14 demonstrate the execution of the RET (1-byte, three cycles) instruction. In Figure 5-13, the return address
resides on the same 256-byte page as that of the executed RET instruction. Two stall cycles are inserted followed by a page-hit mem-
ory cycle. In Figure 5-14, the return address is on a different 256-byte page from where the RET instruction was executed. In this case,
two stall cycles are inserted, followed by a page-miss memory cycle.
STALL STALL
SYSCLK
ALE
PSEN
PORT 2
PORT 0
ACALL
22
MISS HIT
LSB ADDRESS LSB ADDRESS MSB ADDRESS LSB ADDRESS
Figure 5-14. Four-Cycle Page Mode 1: RET – (Page Miss)
SYSCLK
ALE
PSEN
PORT 2
PORT 0 22
HIT HIT HIT STALL STALL
RET
LSB ADDRESS LSB ADDRESS LSB ADDRESS LSB ADDRESS
Figure 5-13. Four-Cycle Page Mode 1: RET
Ultra-High-Speed Flash
Microcontroller User’s Guide
Maxim Integrated