Altera Arria 10 Avalon-ST User Manual
Page 93
Header 3
Data 2
Header 2
Data 1
Data n
Header 1
Data 0
Data n-1
Header 0
Data n-2
pld_clk
tx_st_valid
tx_st_data[127:96]
tx_st_data[95:64]
tx_st_data[63:32]
tx_st_data[31:0]
tx_st_sop
tx_st_eop
tx_st_empty
Figure 6-28: 128-Bit Back-to-Back Transmission on the Avalon-ST TX Interface
The following figure illustrates back-to-back transmission of 128-bit packets with idle dead cycles between
the assertion of
tx_st_eop
and
tx_st_sop
.
pld_clk
tx_st_data[127:0]
tx_st_sop
tx_st_eop
tx_st_empty
tx_st_ready
tx_st_valid
tx_st_err
.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-29: 128-Bit Hard IP Backpressures the Application Layer for TX Transactions
The following figure illustrates the timing of the TX interface when the Arria 10 Hard IP for PCI Express
pauses the Application Layer by deasserting
tx_st_ready
. Because the
readyLatency
is two cycles, the
Application Layer deasserts
tx_st_valid
after two cycles and holds
tx_st_data
until two cycles after
tx_st_ready
is reasserted
UG-01145_avst
2015.05.04
Data Alignment and Timing for the 128‑Bit Avalon‑ST TX Interface
6-27
Interfaces and Signal Descriptions
Altera Corporation