Qsys design flow, Qsys design flow -2 – Altera Arria 10 Avalon-ST User Manual
Page 21
For a detailed explanation of this example design, refer to the Testbench and Design Example chapter. If
you choose the parameters specified in this chapter, you can run all of the tests included in Testbench and
Design Example chapter.
For more information about Qsys, refer to System Design with Qsys in the Quartus II Handbook. For more
information about the Qsys GUI, refer to About Qsys in Quartus II Help.
Related Information
•
on page 17-1
•
Understanding Simulation Log File Generation
on page 2-4
•
•
Qsys Design Flow
Copy the ep_g1x8.qsys design example from the
a10_ed/example_designs/a10
to your working directory.
The following figure illustrates this Qsys system.
Figure 2-2: Complete Gen1 ×8 Endpoint (DUT) Connected to Example Design (APPS)
2-2
Qsys Design Flow
UG-01145_avst
2015.05.04
Altera Corporation
Getting Started with the Arria 10 Hard IP for PCI Express
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