Altera Arria 10 Avalon-ST User Manual
Page 11
Feature
Avalon-ST Interface
Avalon-MM
Interface
Avalon-MM DMA
Avalon-ST Interface with SR-
IOV
Automatically
handle out-of-
order
completions
(transparent to
the Application
Layer)
Not supported
Supported
Supported
Not supported
Automatically
handle requests
that cross 4
KByte address
boundary
(transparent to
the Application
Layer)
Not supported
Supported
Supported
Not Supported
Polarity
Inversion of
PIPE interface
signals
Supported
Supported
Supported
Supported
Number of MSI
requests
1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 (for
Physical Functions)
MSI-X
Supported
Supported
Supported
Supported
Legacy
interrupts
Supported
Supported
Supported
Supported
Expansion
ROM
Supported
Not supported
Not supported
Not supported
Table 1-3: TLP Support Comparison for all Hard IP for PCI Express IP Cores
The table compares the TLP types that the four Hard IP for PCI Express IP Cores can transmit. Each entry
indicates whether this TLP type is supported (for transmit) by endpoints (EP), Root Ports (RP), or both (EP/RP).
Transaction Layer
Packet type (TLP)
(transmit support)
Avalon-ST Interface
Avalon-MM
Interface
Avalon-MM DMA
Avalon-ST Interface with SR-
IOV
Memory Read
Request (
Mrd
)
EP/RP
EP/RP
EP
EP
1-4
Arria 10 Features
UG-01145_avst
2015.05.04
Altera Corporation
Datasheet